Non-volatile memory devices continuously hold data even when an external power is turned off. As the integration density of memory devices increases, there is a need for reducing the area and vertical height of a memory cell. Since a conventional floating gate type non-volatile memory device has a floating gate, it is restrictive to reduce a vertical height of a memory cell. For that reason, a floating trap-type non-volatile memory device has been attractive as a candidate to overcome the above disadvantage in that charges can be stored in at least one insulating layer without a floating gate.
FIG. 1 is a top plan view of a conventional floating trap-type non-volatile memory device. A device isolation layer 11 is formed in a predetermined area of a semiconductor substrate to define an active region 13. A plurality of gate electrodes 30 cross the active region, and a charge storage layer 24 is intervened between the gate electrode 30 and the active region 13. A sidewall spacer 36 is formed on a sidewall of the gate electrode 30.
FIG. 2 through FIG. 5 are cross-sectional flow diagrams showing the steps of fabricating a conventional non-volatile memory device, taken along a line I–I′ of FIG. 1.
Referring now to FIG. 2, a device isolation layer 11 is formed in a predetermined area of a semiconductor substrate to define active regions 13. A stack insulating layer 18 and a gate conductive layer 20 are formed on a semiconductor substrate where the device isolation layer 11 is formed. Generally, the stack insulating layer 18 includes first, second, and third insulating layers 12, 14, and 16 which are conventionally made of thin thermal oxide, silicon nitride, and CVD oxide, respectively.
Referring now to FIG. 3, the gate conductive layer 20 and the stack insulating layer 18 are sequentially patterned to form a plurality of gate electrodes 30 crossing the device isolation layer 11. A tunnel oxide layer 22, a charge storage layer 24, and a blocking insulating layer 26 are sequentially stacked between the gate electrode 30 and the active region 13. In case sidewalls of the tunnel oxide layer 22, the charge storage layer 24, and the blocking insulating layer 26 are damaged by an etch, a defect density increases with increased trap density around edges of the tunnel oxide layer 22 and the blocking insulating layer 26. As a result, it is likely to generate a trap-assisted leakage current to the gate electrode 30 and the semiconductor substrate 10 through the high-density trap.
Referring now to FIG. 4, a thermal oxidation process is carried out for the semiconductor substrate in order to alleviate the damage of the sidewalls of the blocking insulating layer 26 and the gate electrode 30. As a result, a capping insulating layer 32 is formed on a sidewall and a top surface of the gate electrode 30.
Referring now to FIG. 5, using the gate electrode 30 and the capping insulating layer 32 as an ion implanting mask, impurities are implanted into the semiconductor substrate to form an impurity diffusion layer 34. A sidewall spacer 36 is then formed on sidewalls of the charge storage layer 24, the blocking insulating layer 26, and the capping insulating layer 32 that are sequentially stacked. As illustrated in FIG. 4 and FIG. 5, oxygen atoms are diffused through an interface between the semiconductor substrate 10 and the tunnel oxide layer 22 during the thermal oxidation process. At this time, an edge of the tunnel oxide layer 22 becomes thick (i.e., a bird's beak phenomenon occurs) because it is oxidized by the diffused oxygen atoms. This leads to a drop in device operational speed. Furthermore, a trap density becomes high at the relatively thicker edge of the tunneling oxide layer 22 thereby increasing trap-assisted leakage current through the edge. As the bird's beak phenomenon causes a thickness variation of a tunnel oxide layer to be high in a cell array, device characteristics become non-uniform. The more a gate line width decreases, the more the thickness of the tunnel oxide layer 22 increases. Therefore, what is needed is a non-volatile memory device with a structure to overcome device operational characteristic defects that result from a tunnel oxide layer of high trap density and from bird's beak phenomenon.